Method wait

src/platforms/arm/lpc/rx_sct_capture.cpp.hpp:544–627

}

RxWaitResult LpcSctRxChannel::wait(u32 timeout_ms) FL_NOEXCEPT {
#if defined(FASTLED_LPC_RX_SCT_DMA) && defined(FL_IS_ARM_LPC_845)
    // DMA capture path. The two DMA channels are autonomously latching
    // SCT->CAP[0..1] into the rings via the SCT_DMAn trigger lines —
    // CPU just sleeps for the capture window, then halts the SCT and
    // merges the two rings by timestamp into mEdges.
    //
    // ---- 1. Sleep for the capture window. ----
    const fl::u32 start_ms = millis();
    while ((millis() - start_ms) < timeout_ms) {
        const fl::u32 rising_done  = dmaChannelEdgeCount(0);
        const fl::u32 falling_done = dmaChannelEdgeCount(1);
        if (rising_done >= kDmaRingSize && falling_done >= kDmaRingSize) {
            break;  // both rings full — no point waiting longer
        }
        // No need to spin tight; the DMA work happens in hardware.
        // A small idle keeps wakelet contention down. (millis() based
        // throttle — we don't need precise pacing here.)
    }

    // ---- 2. Halt SCT to stop further captures. ----
    sct(kOffCTRL) |= kCtrlHaltL;

    // ---- 3. Snapshot how many entries each ring received. ----
    const fl::u32 n_rising  = dmaChannelEdgeCount(0);
    const fl::u32 n_falling = dmaChannelEdgeCount(1);

    // Disable channels so SETVALID can re-arm in the next begin().
    dma(kOffDmaEnableClr0) = (1u << 0) | (1u << 1);

    // ---- 4. Merge the two rings by timestamp into mEdges. ----
    // The rings hold raw 32-bit SCT counter ticks. Walk both in parallel
    // (they're already monotonic per-direction), pick the earlier tick,
    // emit `EdgeTime{level, ns-delta-from-prior}`.
    fl::u32 ir = 0, jf = 0;
    fl::u32 prev_tick = 0;
    bool prev_seen = false;
    bool last_was_rising = false;
    while (ir < n_rising || jf < n_falling) {
        if (mEdges.size() >= mCapacity) break;

        bool pick_rising;
        if (ir >= n_rising) {
            pick_rising = false;
        } else if (jf >= n_falling) {
            pick_rising = true;
        } else {
            // Both rings have unread entries; pick the earlier tick.
            // Unsigned subtract treats wrap as modulo — assume neither
            // ring's outstanding entries span a full 32-bit wrap (~143 s
            // at 30 MHz, way beyond our test windows).
            pick_rising = (g_dma_rising[ir] - g_dma_falling[jf]) >= 0x80000000u;
        }

        const fl::u32 tick = pick_rising ? g_dma_rising[ir] : g_dma_falling[jf];
        if (prev_seen) {
            const fl::u32 delta = tick - prev_tick;
            mEdges.push_back(EdgeTime(last_was_rising, ticksToNs(delta)));