| 473 | } |
| 474 | |
| 475 | bool SPIQuadSAMD51::waitComplete(u32 timeout_ms) { |
| 476 | if (!mTransactionActive) { |
| 477 | return true; // Nothing to wait for |
| 478 | } |
| 479 | |
| 480 | // Implementation Note: |
| 481 | // Current transmit() implementation is synchronous (polling-based), |
| 482 | // waiting for QSPI INSTREND flag before returning. |
| 483 | // Therefore, by the time waitComplete() is called, the transaction |
| 484 | // is already complete. |
| 485 | // |
| 486 | // This timeout logic is provided for API consistency and future-proofing |
| 487 | // in case async DMA implementation is added later. |
| 488 | |
| 489 | fl::u32 start_time = fl::millis(); |
| 490 | |
| 491 | // Poll QSPI status to verify transmission actually completed |
| 492 | // Check INSTREND (Instruction End) flag in INTFLAG register |
| 493 | while (!QSPI->INTFLAG.bit.INSTREND) { |
| 494 | if ((fl::millis() - start_time) >= timeout_ms) { |
| 495 | FL_WARN("SPIQuadSAMD51: waitComplete timeout"); |
| 496 | return false; // Timeout |
| 497 | } |
| 498 | // Check for error condition |
| 499 | if (QSPI->INTFLAG.bit.ERROR) { |
| 500 | FL_WARN("SPIQuadSAMD51: QSPI error during waitComplete"); |
| 501 | QSPI->INTFLAG.reg = QSPI_INTFLAG_ERROR; // Clear error |
| 502 | return false; |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | mTransactionActive = false; |
| 507 | |
| 508 | // AUTO-RELEASE DMA buffer |
| 509 | mBufferAcquired = false; |
| 510 | mCurrentTotalSize = 0; |
| 511 | |
| 512 | return true; |
| 513 | } |
| 514 | |
| 515 | bool SPIQuadSAMD51::isBusy() const { |
| 516 | if (!mInitialized) { |