Test behavior with zero timing values.
(self)
| 311 | """Test edge cases and error handling.""" |
| 312 | |
| 313 | def test_zero_timing_values(self) -> None: |
| 314 | """Test behavior with zero timing values.""" |
| 315 | # T3 can be zero (some chipsets have no tail time) |
| 316 | ds = TimingDatasheet(T0H=400, T0L=850, T1H=850, T1L=400) |
| 317 | fl = datasheet_to_phase3(ds) |
| 318 | self.assertIsNotNone(fl) |
| 319 | |
| 320 | # But T1 and T2 should not be zero in practice |
| 321 | # (though mathematically valid) |
| 322 | |
| 323 | def test_asymmetric_cycles(self) -> None: |
| 324 | """Test chipsets where T0H+T0L ≠ T1H+T1L.""" |
nothing calls this directly
no test coverage detected