Method test_asymmetric_cycles

ci/test_led_timing_conversion.py:323–340

Test chipsets where T0H+T0L ≠ T1H+T1L.

(self)

        # (though mathematically valid)

    def test_asymmetric_cycles(self) -> None:
        """Test chipsets where T0H+T0L ≠ T1H+T1L."""
        # This happens when duration = max(cycle_0, cycle_1)
        ds = TimingDatasheet(
            T0H=250,
            T0L=500,  # cycle_0 = 750
            T1H=875,
            T1L=875,  # cycle_1 = 1750
            name="Asymmetric",
        )

        fl = datasheet_to_phase3(ds)

        # Duration should be max(750, 1750) = 1750
        self.assertEqual(fl.duration, 1750)
        self.assertEqual(fl.T1, 250)
        self.assertEqual(fl.T2, 625)
        self.assertEqual(fl.T3, 875)  # 1750 - 875

    def test_invalid_inverse_conversion(self) -> None:
        """Test inverse conversion with invalid inputs."""