| 327 | // Implementation of inline ISR-safe primitives |
| 328 | |
| 329 | inline void transpose_2lane_inline( |
| 330 | const u8* lane0_byte, |
| 331 | const u8* lane1_byte, |
| 332 | u8* output, |
| 333 | size_t num_bytes |
| 334 | ) FL_NOEXCEPT { |
| 335 | for (size_t byte_idx = 0; byte_idx < num_bytes; byte_idx++) { |
| 336 | u8 a = lane0_byte[byte_idx]; |
| 337 | u8 b = lane1_byte[byte_idx]; |
| 338 | |
| 339 | // dest[0] contains bit pairs for positions 7,6,5,4 (MSB first) |
| 340 | output[byte_idx * 2 + 0] = |
| 341 | ((a >> 7) & 0x01) << 0 | ((b >> 7) & 0x01) << 1 | |
| 342 | ((a >> 6) & 0x01) << 2 | ((b >> 6) & 0x01) << 3 | |
| 343 | ((a >> 5) & 0x01) << 4 | ((b >> 5) & 0x01) << 5 | |
| 344 | ((a >> 4) & 0x01) << 6 | ((b >> 4) & 0x01) << 7; |
| 345 | |
| 346 | // dest[1] contains bit pairs for positions 3,2,1,0 (LSB) |
| 347 | output[byte_idx * 2 + 1] = |
| 348 | ((a >> 3) & 0x01) << 0 | ((b >> 3) & 0x01) << 1 | |
| 349 | ((a >> 2) & 0x01) << 2 | ((b >> 2) & 0x01) << 3 | |
| 350 | ((a >> 1) & 0x01) << 4 | ((b >> 1) & 0x01) << 5 | |
| 351 | ((a >> 0) & 0x01) << 6 | ((b >> 0) & 0x01) << 7; |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | inline void transpose_4lane_inline( |
| 356 | const u8* const lanes[4], |