| 41 | |
| 42 | /// Platform-agnostic configuration structure for 8-lane SPI |
| 43 | struct Config { |
| 44 | u8 bus_num; ///< SPI bus number (platform-specific numbering) |
| 45 | u32 clock_speed_hz; ///< Clock frequency in Hz |
| 46 | i8 clock_pin; ///< SCK GPIO pin |
| 47 | i8 data0_pin; ///< D0/MOSI GPIO pin |
| 48 | i8 data1_pin; ///< D1 GPIO pin |
| 49 | i8 data2_pin; ///< D2 GPIO pin |
| 50 | i8 data3_pin; ///< D3 GPIO pin |
| 51 | i8 data4_pin; ///< D4 GPIO pin |
| 52 | i8 data5_pin; ///< D5 GPIO pin |
| 53 | i8 data6_pin; ///< D6 GPIO pin |
| 54 | i8 data7_pin; ///< D7 GPIO pin |
| 55 | u32 max_transfer_sz; ///< Max bytes per transfer |
| 56 | |
| 57 | Config() |
| 58 | FL_NOEXCEPT : bus_num(0) |
| 59 | , clock_speed_hz(20000000) |
| 60 | , clock_pin(-1) |
| 61 | , data0_pin(-1) |
| 62 | , data1_pin(-1) |
| 63 | , data2_pin(-1) |
| 64 | , data3_pin(-1) |
| 65 | , data4_pin(-1) |
| 66 | , data5_pin(-1) |
| 67 | , data6_pin(-1) |
| 68 | , data7_pin(-1) |
| 69 | , max_transfer_sz(65536) {} |
| 70 | }; |
| 71 | |
| 72 | /// Initialize SPI peripheral with given configuration |
| 73 | /// @param config Hardware configuration (all 8 data pins must be valid) |