Class ClocklessController

src/platforms/arm/lpc/clockless_arm_lpc_plu.h:296–400

template <fl::u8 DATA_PIN, typename TIMING, EOrder RGB_ORDER = RGB,
          int XTRA0 = 0, bool FLIP = false, int WAIT_TIME = 280>
class ClocklessController : public CPixelLEDController<RGB_ORDER> {
    typedef typename FastPin<DATA_PIN>::port_ptr_t data_ptr_t;
    typedef typename FastPin<DATA_PIN>::port_t     data_t;

    data_t     mPinMask;
    data_ptr_t mPort;
    CMinWait<WAIT_TIME> mWait;
    bool       mPluReady;

public:
    ClocklessController() FL_NOEXCEPT : mPinMask(0), mPort(0), mPluReady(false) {}

    virtual void init() FL_NOEXCEPT {
        // The CPU still owns the data pin - the PLU samples it via SWM, but
        // the pin itself is a normal GPIO that the CPU writes to.
        FastPin<DATA_PIN>::setOutput();
        mPinMask = FastPin<DATA_PIN>::mask();
        mPort    = FastPin<DATA_PIN>::port();

        // Program the PLU LUT graph once. Idempotent.
        lpc_plu_detail::initPluGraph();
        mPluReady = true;
    }

    virtual fl::u16 getMaxRefreshRate() const { return 400; }

    virtual void showPixels(PixelController<RGB_ORDER>& pixels) FL_NOEXCEPT {
        mWait.wait();

        // The PLU drives the wire shape; the CPU's only job is to clock data
        // bits out at the bit-rate cadence. We disable interrupts during the
        // transfer because a long ISR could stretch a single bit past the
        // WS2812 reset threshold (>50us) and end the frame prematurely.
        cli();
        feedPixels(pixels);
        sei();

        mWait.mark();
    }

private:
    // Feed every bit of every pixel into the PLU's data-input GPIO.
    //
    // Per-bit cadence:
    //   1. The PLU's timing counter is free-running on its own clock domain.
    //   2. The CPU samples the next data bit, writes it to the data GPIO.
    //   3. The PLU latches the resulting bit-window output on each counter
    //      rollover. We must guarantee the new DATA value is stable BEFORE
    //      the rollover edge that begins the bit.
    //
    // Synchronisation strategy:
    //   We do not poll the timing counter; we just push bits at slightly
    //   below the bit-rate. The PLU samples DATA at each rising edge of its
    //   internal bit-period clock; as long as we update DATA between
    //   rollovers, the LED stream is correct. At 15 MHz CPU and ~1.25us
    //   per WS2812 bit, that's ~18 cycles of slack per bit - plenty.
    //
    // TODO(2841): once the SCT-based timing source is integrated, expose a