@brief Configuration for SPI device (supports 1-8 lanes)
| 42 | |
| 43 | /// @brief Configuration for SPI device (supports 1-8 lanes) |
| 44 | struct SpiConfig { |
| 45 | SpiConfig() FL_NOEXCEPT = default; |
| 46 | |
| 47 | /// @brief Construct single-lane SPI config |
| 48 | SpiConfig(int clk, int data, u32 speed_hz = 0xffffffff, spi_output_mode_t output_mode = spi_output_mode_t::SPI_AUTO, u8 spi_mode = 0) |
| 49 | : clock_pin(clk) |
| 50 | , clock_speed_hz(speed_hz) |
| 51 | , output_mode(output_mode) |
| 52 | , spi_mode(spi_mode) { |
| 53 | data_pins.push_back(data); |
| 54 | } |
| 55 | |
| 56 | /// @brief Construct multi-lane SPI config |
| 57 | SpiConfig(int clk, fl::span<const int> pins, u32 speed_hz = 0xffffffff, spi_output_mode_t output_mode = spi_output_mode_t::SPI_AUTO, u8 spi_mode = 0) |
| 58 | : clock_pin(clk) |
| 59 | , clock_speed_hz(speed_hz) |
| 60 | , output_mode(output_mode) |
| 61 | , spi_mode(spi_mode) { |
| 62 | // Manually copy pins to data_pins vector |
| 63 | for (size_t i = 0; i < pins.size(); i++) { |
| 64 | data_pins.push_back(pins[i]); |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | /// @brief Check if this is a multi-lane configuration |
| 69 | bool isMultiLane() const { return data_pins.size() > 1; } |
| 70 | |
| 71 | int clock_pin; ///< SCK pin number |
| 72 | fl::vector<int> data_pins; ///< Data pins (1 = single-lane, 2-8 = multi-lane) |
| 73 | u32 clock_speed_hz = 0xffffffff; ///< Clock frequency in Hz (0xffffffff = as fast as possible) |
| 74 | spi_output_mode_t output_mode = spi_output_mode_t::SPI_AUTO; ///< Output mode (auto/hw/bitbang/isr) |
| 75 | u8 spi_mode = 0; ///< SPI mode 0-3 (CPOL/CPHA) |
| 76 | }; |
| 77 | |
| 78 | namespace spi { |
| 79 |