| 699 | template void OpDispatchBuilder::VectorUnaryDuplicateOp<IR::OP_VFRECPPRECISION, OpSize::i32Bit>(OpcodeArgs); |
| 700 | |
| 701 | void OpDispatchBuilder::MOVQOp(OpcodeArgs, VectorOpType VectorType) { |
| 702 | const auto SrcSize = Op->Src[0].IsGPR() ? OpSize::i128Bit : OpSizeFromSrc(Op); |
| 703 | Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], SrcSize, Op->Flags); |
| 704 | // This instruction is a bit special that if the destination is a register then it'll ZEXT the 64bit source to 128bit |
| 705 | if (Op->Dest.IsGPR()) { |
| 706 | const auto gpr = Op->Dest.Data.GPR.GPR; |
| 707 | const auto gprIndex = gpr - X86State::REG_XMM_0; |
| 708 | |
| 709 | auto Reg = VZeroExtendOperand(OpSize::i64Bit, Op->Src[0], Src); |
| 710 | StoreXMMRegister_WithAVXInsert(VectorType, gprIndex, Reg); |
| 711 | } else { |
| 712 | // This is simple, just store the result |
| 713 | StoreResult(FPRClass, Op, Src, OpSize::iInvalid); |
| 714 | } |
| 715 | } |
| 716 | |
| 717 | void OpDispatchBuilder::MOVQMMXOp(OpcodeArgs) { |
| 718 | // Partial store into bottom 64-bits, leave the upper bits unaffected. |