Method CVTFPR_To_GPRImpl

FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp:2103–2130

template void OpDispatchBuilder::AVXCVTGPR_To_FPR<OpSize::i64Bit>(OpcodeArgs);

Ref OpDispatchBuilder::CVTFPR_To_GPRImpl(OpcodeArgs, Ref Src, IR::OpSize SrcElementSize, bool HostRoundingMode) {
  // GPR size is determined by REX.W
  // Source Element size is determined by instruction
  const auto GPRSize = OpSizeFromDst(Op);

  if (CTX->HostFeatures.SupportsFRINTTS) {
    // When we have FRINTTS, this is a two-step process. First, we round to the
    // right integer (where _Vector_FToISized matches x86 semantics), then just
    // convert that to a GPR.
    Src = _Vector_FToISized(SrcElementSize, SrcElementSize, Src, HostRoundingMode, GPRSize);
    return _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src);
  } else {
    // When we lack hardware support, we need a bit of a convoluted sequence of
    // fixups before before and after conversion to emulate x86 semantics.
    if (HostRoundingMode) {
      Src = _Vector_FToI(SrcElementSize, SrcElementSize, Src, Round_Host);
    }

    Ref Converted = _Float_ToGPR_ZS(GPRSize, SrcElementSize, Src);

    bool Dst32 = GPRSize == OpSize::i32Bit;
    Ref MaxI = Dst32 ? Constant(0x80000000) : Constant(0x8000000000000000);
    Ref MaxF = LoadAndCacheNamedVectorConstant(SrcElementSize, (SrcElementSize == OpSize::i32Bit) ?
                                                                 (Dst32 ? NAMED_VECTOR_CVTMAX_F32_I32 : NAMED_VECTOR_CVTMAX_F32_I64) :
                                                                 (Dst32 ? NAMED_VECTOR_CVTMAX_F64_I32 : NAMED_VECTOR_CVTMAX_F64_I64));
    return _Select(GPRSize, SrcElementSize, CondClassType {FEXCore::IR::COND_FGT}, MaxF, Src, Converted, MaxI);
  }
}

template<IR::OpSize SrcElementSize, bool HostRoundingMode>
void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) {