| 279 | } |
| 280 | |
| 281 | void OpDispatchBuilder::AVXVectorXOROp(OpcodeArgs) { |
| 282 | // Special case for vector xor with itself being the optimal way for x86 to zero vector registers. |
| 283 | if (Op->Src[0].IsGPR() && Op->Src[1].IsGPR() && Op->Src[0].Data.GPR.GPR == Op->Src[1].Data.GPR.GPR) { |
| 284 | const auto DstSize = OpSizeFromDst(Op); |
| 285 | const auto ZeroRegister = LoadZeroVector(DstSize); |
| 286 | StoreResult(FPRClass, Op, ZeroRegister, OpSize::iInvalid); |
| 287 | return; |
| 288 | } |
| 289 | |
| 290 | ///< Regular code path |
| 291 | AVXVectorALUOp(Op, OP_VXOR, OpSize::i128Bit); |
| 292 | } |
| 293 | |
| 294 | void OpDispatchBuilder::VectorALUROp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize) { |
| 295 | const auto Size = OpSizeFromSrc(Op); |