| 268 | } |
| 269 | |
| 270 | void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize) { |
| 271 | const auto Size = OpSizeFromSrc(Op); |
| 272 | |
| 273 | Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags); |
| 274 | Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags); |
| 275 | |
| 276 | DeriveOp(ALUOp, IROp, _VAdd(Size, ElementSize, Src1, Src2)); |
| 277 | |
| 278 | StoreResult(FPRClass, Op, ALUOp, OpSize::iInvalid); |
| 279 | } |
| 280 | |
| 281 | void OpDispatchBuilder::AVXVectorXOROp(OpcodeArgs) { |
| 282 | // Special case for vector xor with itself being the optimal way for x86 to zero vector registers. |
nothing calls this directly
no test coverage detected