| 801 | } |
| 802 | |
| 803 | void Arm64JITCore::EmitEntryPoint(ARMEmitter::BackwardLabel& HeaderLabel, bool CheckTF) { |
| 804 | // Get the address of the JITCodeHeader and store in to the core state. |
| 805 | // Two instruction cost, each 1 cycle. |
| 806 | adr(TMP1, &HeaderLabel); |
| 807 | str(TMP1, STATE, offsetof(FEXCore::Core::CPUState, InlineJITBlockHeader)); |
| 808 | |
| 809 | EmitInterruptChecks(CheckTF); |
| 810 | |
| 811 | if (SpillSlots) { |
| 812 | const auto TotalSpillSlotsSize = SpillSlots * MaxSpillSlotSize; |
| 813 | |
| 814 | if (ARMEmitter::IsImmAddSub(TotalSpillSlotsSize)) { |
| 815 | sub(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, ARMEmitter::Reg::rsp, TotalSpillSlotsSize); |
| 816 | } else { |
| 817 | LoadConstant(ARMEmitter::Size::i64Bit, TMP1, TotalSpillSlotsSize); |
| 818 | sub(ARMEmitter::Size::i64Bit, ARMEmitter::XReg::rsp, ARMEmitter::XReg::rsp, TMP1, ARMEmitter::ExtendedType::LSL_64, 0); |
| 819 | } |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size, bool SingleInst, const FEXCore::IR::IRListView* IR, |
| 824 | FEXCore::Core::DebugData* DebugData, bool CheckTF) { |
nothing calls this directly
no test coverage detected