| 821 | } |
| 822 | |
| 823 | CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size, bool SingleInst, const FEXCore::IR::IRListView* IR, |
| 824 | FEXCore::Core::DebugData* DebugData, bool CheckTF) { |
| 825 | FEXCORE_PROFILE_SCOPED("Arm64::CompileCode"); |
| 826 | |
| 827 | JumpTargets.clear(); |
| 828 | CallReturnTargets.clear(); |
| 829 | PendingJumpThunks.clear(); |
| 830 | uint32_t SSACount = IR->GetSSACount(); |
| 831 | JumpTargets.resize(IR->GetHeader()->BlockCount, {}); |
| 832 | |
| 833 | this->Entry = Entry; |
| 834 | this->DebugData = DebugData; |
| 835 | this->IR = IR; |
| 836 | CodeData.EntryPoints.clear(); |
| 837 | |
| 838 | // Fairly excessive buffer range to make sure we don't overflow |
| 839 | uint32_t BufferRange = 0x1000 + SSACount * 24; |
| 840 | |
| 841 | // JIT output is first written to a temporary buffer and later relocated to the CodeBuffer. |
| 842 | // This minimizes lock contention of CodeBufferWriteMutex. |
| 843 | auto TempCodeBuffer = TempAllocator.ReownOrClaimBuffer(BufferRange); |
| 844 | SetBuffer(TempCodeBuffer, BufferRange); |
| 845 | |
| 846 | CodeData.BlockBegin = GetCursorAddress<uint8_t*>(); |
| 847 | |
| 848 | // Put the code header at the start of the data block. |
| 849 | ARMEmitter::BackwardLabel JITCodeHeaderLabel {}; |
| 850 | Bind(&JITCodeHeaderLabel); |
| 851 | JITCodeHeader* CodeHeader = GetCursorAddress<JITCodeHeader*>(); |
| 852 | CursorIncrement(sizeof(JITCodeHeader)); |
| 853 | |
| 854 | auto CodeBegin = GetCursorAddress<uint8_t*>(); |
| 855 | |
| 856 | // AAPCS64 |
| 857 | // r30 = LR |
| 858 | // r29 = FP |
| 859 | // r19..r28 = Callee saved |
| 860 | // r18 = Platform Register (Matters if we target Windows or iOS) |
| 861 | // r16..r17 = Inter-procedure scratch |
| 862 | // r9..r15 = Temp |
| 863 | // r8 = Indirect Result |
| 864 | // r0...r7 = Parameter/Results |
| 865 | // |
| 866 | // FPRS: |
| 867 | // v8..v15 = (lower 64bits) Callee saved |
| 868 | |
| 869 | // Our allocation: |
| 870 | // X0 = ThreadState |
| 871 | // X1 = MemBase |
| 872 | // |
| 873 | // X1-X3 = Temp |
| 874 | // X4-r18 = RA |
| 875 | |
| 876 | SpillSlots = IR->SpillSlots(); |
| 877 | |
| 878 | PendingTargetLabel = nullptr; |
| 879 | PendingCallReturnTargetLabel = nullptr; |
| 880 |
nothing calls this directly
no test coverage detected