2: Cache and TLB information
| 499 | |
| 500 | // 2: Cache and TLB information |
| 501 | FEXCore::CPUID::FunctionResults CPUIDEmu::Function_02h(uint32_t Leaf) const { |
| 502 | FEXCore::CPUID::FunctionResults Res {}; |
| 503 | |
| 504 | // returns default values from i7 model 1Ah |
| 505 | Res.eax = 0x1 | // Number of iterations needed for all descriptors |
| 506 | (0x5A << 8) | (0x03 << 16) | (0x55 << 24); |
| 507 | |
| 508 | Res.ebx = 0xE4 | (0xB2 << 8) | (0xF0 << 16) | (0 << 24); |
| 509 | |
| 510 | Res.ecx = 0; // null descriptors |
| 511 | |
| 512 | Res.edx = 0x2C | (0x21 << 8) | (0xCA << 16) | (0x09 << 24); |
| 513 | |
| 514 | return Res; |
| 515 | } |
| 516 | |
| 517 | // 4: Deterministic cache parameters for each level |
| 518 | FEXCore::CPUID::FunctionResults CPUIDEmu::Function_04h(uint32_t Leaf) const { |
nothing calls this directly
no outgoing calls
no test coverage detected