Function DEF_OP

FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp:20–50

namespace FEXCore::CPU {

DEF_OP(LoadContext) {
  const auto Op = IROp->C<IR::IROp_LoadContext>();
  const auto OpSize = IROp->Size;

  if (Op->Class == FEXCore::IR::GPRClass) {
    auto Dst = GetReg(Node);

    switch (OpSize) {
    case IR::OpSize::i8Bit: ldrb(Dst, STATE, Op->Offset); break;
    case IR::OpSize::i16Bit: ldrh(Dst, STATE, Op->Offset); break;
    case IR::OpSize::i32Bit: ldr(Dst.W(), STATE, Op->Offset); break;
    case IR::OpSize::i64Bit: ldr(Dst.X(), STATE, Op->Offset); break;
    default: LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize); break;
    }
  } else {
    auto Dst = GetVReg(Node);

    switch (OpSize) {
    case IR::OpSize::i8Bit: ldrb(Dst, STATE, Op->Offset); break;
    case IR::OpSize::i16Bit: ldrh(Dst, STATE, Op->Offset); break;
    case IR::OpSize::i32Bit: ldr(Dst.S(), STATE, Op->Offset); break;
    case IR::OpSize::i64Bit: ldr(Dst.D(), STATE, Op->Offset); break;
    case IR::OpSize::i128Bit: ldr(Dst.Q(), STATE, Op->Offset); break;
    case IR::OpSize::i256Bit:
      mov(TMP1, Op->Offset);
      ld1b<ARMEmitter::SubRegSize::i8Bit>(Dst.Z(), PRED_TMP_32B.Zeroing(), STATE, TMP1);
      break;
    default: LOGMAN_MSG_A_FMT("Unhandled LoadContext size: {}", OpSize); break;
    }
  }
}

DEF_OP(LoadContextPair) {
  const auto Op = IROp->C<IR::IROp_LoadContextPair>();