| 92 | } |
| 93 | |
| 94 | struct ThreadCPUArea { |
| 95 | static constexpr size_t TEBCPUAreaOffset = 0x1788; |
| 96 | CHPE_V2_CPU_AREA_INFO* Area; |
| 97 | |
| 98 | explicit ThreadCPUArea(_TEB* TEB) |
| 99 | : Area(*reinterpret_cast<CHPE_V2_CPU_AREA_INFO**>(reinterpret_cast<uintptr_t>(TEB) + TEBCPUAreaOffset)) {} |
| 100 | |
| 101 | uint64_t& EmulatorStackLimit() const { |
| 102 | return Area->EmulatorStackLimit; |
| 103 | } |
| 104 | |
| 105 | uint64_t& EmulatorStackBase() const { |
| 106 | return Area->EmulatorStackBase; |
| 107 | } |
| 108 | |
| 109 | ARM64EC_NT_CONTEXT& ContextAmd64() const { |
| 110 | return *Area->ContextAmd64; |
| 111 | } |
| 112 | |
| 113 | FEXCore::Core::CpuStateFrame*& StateFrame() const { |
| 114 | return reinterpret_cast<FEXCore::Core::CpuStateFrame*&>(Area->EmulatorData[0]); |
| 115 | } |
| 116 | |
| 117 | FEXCore::Core::InternalThreadState*& ThreadState() const { |
| 118 | return reinterpret_cast<FEXCore::Core::InternalThreadState*&>(Area->EmulatorData[1]); |
| 119 | } |
| 120 | |
| 121 | uint64_t& DispatcherLoopTopEnterEC() const { |
| 122 | return reinterpret_cast<uint64_t&>(Area->EmulatorData[2]); |
| 123 | } |
| 124 | |
| 125 | uint64_t& DispatcherLoopTopEnterECFillSRA() const { |
| 126 | return reinterpret_cast<uint64_t&>(Area->EmulatorData[3]); |
| 127 | } |
| 128 | }; |
| 129 | |
| 130 | namespace { |
| 131 | fextl::unique_ptr<FEXCore::Context::Context> CTX; |
no outgoing calls
no test coverage detected