| 335 | } |
| 336 | |
| 337 | void |
| 338 | init_TSC(void) |
| 339 | { |
| 340 | |
| 341 | if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) |
| 342 | return; |
| 343 | |
| 344 | #ifdef __i386__ |
| 345 | /* The TSC is known to be broken on certain CPUs. */ |
| 346 | switch (cpu_vendor_id) { |
| 347 | case CPU_VENDOR_AMD: |
| 348 | switch (cpu_id & 0xFF0) { |
| 349 | case 0x500: |
| 350 | /* K5 Model 0 */ |
| 351 | return; |
| 352 | } |
| 353 | break; |
| 354 | case CPU_VENDOR_CENTAUR: |
| 355 | switch (cpu_id & 0xff0) { |
| 356 | case 0x540: |
| 357 | /* |
| 358 | * http://www.centtech.com/c6_data_sheet.pdf |
| 359 | * |
| 360 | * I-12 RDTSC may return incoherent values in EDX:EAX |
| 361 | * I-13 RDTSC hangs when certain event counters are used |
| 362 | */ |
| 363 | return; |
| 364 | } |
| 365 | break; |
| 366 | case CPU_VENDOR_NSC: |
| 367 | switch (cpu_id & 0xff0) { |
| 368 | case 0x540: |
| 369 | if ((cpu_id & CPUID_STEPPING) == 0) |
| 370 | return; |
| 371 | break; |
| 372 | } |
| 373 | break; |
| 374 | } |
| 375 | #endif |
| 376 | |
| 377 | probe_tsc_freq(); |
| 378 | |
| 379 | /* |
| 380 | * Inform CPU accounting about our boot-time clock rate. This will |
| 381 | * be updated if someone loads a cpufreq driver after boot that |
| 382 | * discovers a new max frequency. |
| 383 | */ |
| 384 | if (tsc_freq != 0) |
| 385 | set_cputicker(rdtsc, tsc_freq, !tsc_is_invariant); |
| 386 | |
| 387 | if (tsc_is_invariant) |
| 388 | return; |
| 389 | |
| 390 | /* Register to find out about changes in CPU frequency. */ |
| 391 | tsc_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change, |
| 392 | tsc_freq_changing, NULL, EVENTHANDLER_PRI_FIRST); |
| 393 | tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, |
| 394 | tsc_freq_changed, NULL, EVENTHANDLER_PRI_FIRST); |
no test coverage detected