| 717 | } |
| 718 | |
| 719 | static void |
| 720 | amd_thresholding_update(enum scan_mode mode, int bank, int valid) |
| 721 | { |
| 722 | struct amd_et_state *cc; |
| 723 | uint64_t misc; |
| 724 | int new_threshold; |
| 725 | int count; |
| 726 | |
| 727 | cc = &amd_et_state[PCPU_GET(cpuid)][bank]; |
| 728 | misc = rdmsr(mca_msr_ops.misc(bank)); |
| 729 | count = (misc & MC_MISC_AMD_CNT_MASK) >> MC_MISC_AMD_CNT_SHIFT; |
| 730 | count = count - (MC_MISC_AMD_CNT_MAX - cc->cur_threshold); |
| 731 | |
| 732 | new_threshold = update_threshold(mode, valid, cc->last_intr, count, |
| 733 | cc->cur_threshold, MC_MISC_AMD_CNT_MAX); |
| 734 | |
| 735 | cc->cur_threshold = new_threshold; |
| 736 | misc &= ~MC_MISC_AMD_CNT_MASK; |
| 737 | misc |= (uint64_t)(MC_MISC_AMD_CNT_MAX - cc->cur_threshold) |
| 738 | << MC_MISC_AMD_CNT_SHIFT; |
| 739 | misc &= ~MC_MISC_AMD_OVERFLOW; |
| 740 | wrmsr(mca_msr_ops.misc(bank), misc); |
| 741 | if (mode == CMCI && valid) |
| 742 | cc->last_intr = time_uptime; |
| 743 | } |
| 744 | #endif |
| 745 | |
| 746 | /* |
no test coverage detected