* identifycyrix() set lower 16 bits of cyrix_did as follows: * * F E D C B A 9 8 7 6 5 4 3 2 1 0 * +-------+-------+---------------+ * | SID | RID | Device ID | * | (DIR 1) | (DIR 0) | * +-------+-------+---------------+ */
| 1286 | * +-------+-------+---------------+ |
| 1287 | */ |
| 1288 | static void |
| 1289 | identifycyrix(void) |
| 1290 | { |
| 1291 | register_t saveintr; |
| 1292 | int ccr2_test = 0, dir_test = 0; |
| 1293 | u_char ccr2, ccr3; |
| 1294 | |
| 1295 | saveintr = intr_disable(); |
| 1296 | |
| 1297 | ccr2 = read_cyrix_reg(CCR2); |
| 1298 | write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); |
| 1299 | read_cyrix_reg(CCR2); |
| 1300 | if (read_cyrix_reg(CCR2) != ccr2) |
| 1301 | ccr2_test = 1; |
| 1302 | write_cyrix_reg(CCR2, ccr2); |
| 1303 | |
| 1304 | ccr3 = read_cyrix_reg(CCR3); |
| 1305 | write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); |
| 1306 | read_cyrix_reg(CCR3); |
| 1307 | if (read_cyrix_reg(CCR3) != ccr3) |
| 1308 | dir_test = 1; /* CPU supports DIRs. */ |
| 1309 | write_cyrix_reg(CCR3, ccr3); |
| 1310 | |
| 1311 | if (dir_test) { |
| 1312 | /* Device ID registers are available. */ |
| 1313 | cyrix_did = read_cyrix_reg(DIR1) << 8; |
| 1314 | cyrix_did += read_cyrix_reg(DIR0); |
| 1315 | } else if (ccr2_test) |
| 1316 | cyrix_did = 0x0010; /* 486S A-step */ |
| 1317 | else |
| 1318 | cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ |
| 1319 | |
| 1320 | intr_restore(saveintr); |
| 1321 | } |
| 1322 | #endif |
| 1323 | |
| 1324 | /* Update TSC freq with the value indicated by the caller. */ |
no test coverage detected