| 154 | } |
| 155 | |
| 156 | int |
| 157 | timer_spkr_acquire(void) |
| 158 | { |
| 159 | int mode; |
| 160 | |
| 161 | mode = TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT; |
| 162 | |
| 163 | if (timer2_state != RELEASED) |
| 164 | return (-1); |
| 165 | timer2_state = ACQUIRED; |
| 166 | |
| 167 | /* |
| 168 | * This access to the timer registers is as atomic as possible |
| 169 | * because it is a single instruction. We could do better if we |
| 170 | * knew the rate. Use of splclock() limits glitches to 10-100us, |
| 171 | * and this is probably good enough for timer2, so we aren't as |
| 172 | * careful with it as with timer0. |
| 173 | */ |
| 174 | outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); |
| 175 | |
| 176 | ppi_spkr_on(); /* enable counter2 output to speaker */ |
| 177 | return (0); |
| 178 | } |
| 179 | |
| 180 | int |
| 181 | timer_spkr_release(void) |
no test coverage detected