* Flush the chipset write buffers. See 11.1 "Write Buffer Flushing" * in the architecture specification. */
| 472 | * in the architecture specification. |
| 473 | */ |
| 474 | int |
| 475 | dmar_flush_write_bufs(struct dmar_unit *unit) |
| 476 | { |
| 477 | int error; |
| 478 | |
| 479 | DMAR_ASSERT_LOCKED(unit); |
| 480 | |
| 481 | /* |
| 482 | * DMAR_GCMD_WBF is only valid when CAP_RWBF is reported. |
| 483 | */ |
| 484 | KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, |
| 485 | ("dmar%d: no RWBF", unit->iommu.unit)); |
| 486 | |
| 487 | dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF); |
| 488 | DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) |
| 489 | != 0)); |
| 490 | return (error); |
| 491 | } |
| 492 | |
| 493 | int |
| 494 | dmar_enable_translation(struct dmar_unit *unit) |
no test coverage detected