| 330 | } |
| 331 | |
| 332 | void |
| 333 | intel_hwpstate_identify(driver_t *driver, device_t parent) |
| 334 | { |
| 335 | if (device_find_child(parent, "hwpstate_intel", -1) != NULL) |
| 336 | return; |
| 337 | |
| 338 | if (cpu_vendor_id != CPU_VENDOR_INTEL) |
| 339 | return; |
| 340 | |
| 341 | if (resource_disabled("hwpstate_intel", 0)) |
| 342 | return; |
| 343 | |
| 344 | /* |
| 345 | * Intel SDM 14.4.1 (HWP Programming Interfaces): |
| 346 | * Availability of HWP baseline resource and capability, |
| 347 | * CPUID.06H:EAX[bit 7]: If this bit is set, HWP provides several new |
| 348 | * architectural MSRs: IA32_PM_ENABLE, IA32_HWP_CAPABILITIES, |
| 349 | * IA32_HWP_REQUEST, IA32_HWP_STATUS. |
| 350 | */ |
| 351 | if ((cpu_power_eax & CPUTPM1_HWP) == 0) |
| 352 | return; |
| 353 | |
| 354 | if (BUS_ADD_CHILD(parent, 10, "hwpstate_intel", -1) == NULL) |
| 355 | return; |
| 356 | |
| 357 | if (bootverbose) |
| 358 | device_printf(parent, "hwpstate registered\n"); |
| 359 | } |
| 360 | |
| 361 | static int |
| 362 | intel_hwpstate_probe(device_t dev) |
no test coverage detected