| 3599 | } |
| 3600 | |
| 3601 | static void |
| 3602 | iflib_tx_desc_free(iflib_txq_t txq, int n) |
| 3603 | { |
| 3604 | uint32_t qsize, cidx, mask, gen; |
| 3605 | struct mbuf *m, **ifsd_m; |
| 3606 | bool do_prefetch; |
| 3607 | |
| 3608 | cidx = txq->ift_cidx; |
| 3609 | gen = txq->ift_gen; |
| 3610 | qsize = txq->ift_size; |
| 3611 | mask = qsize-1; |
| 3612 | ifsd_m = txq->ift_sds.ifsd_m; |
| 3613 | do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); |
| 3614 | |
| 3615 | while (n-- > 0) { |
| 3616 | if (do_prefetch) { |
| 3617 | prefetch(ifsd_m[(cidx + 3) & mask]); |
| 3618 | prefetch(ifsd_m[(cidx + 4) & mask]); |
| 3619 | } |
| 3620 | if ((m = ifsd_m[cidx]) != NULL) { |
| 3621 | prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); |
| 3622 | if (m->m_pkthdr.csum_flags & CSUM_TSO) { |
| 3623 | bus_dmamap_sync(txq->ift_tso_buf_tag, |
| 3624 | txq->ift_sds.ifsd_tso_map[cidx], |
| 3625 | BUS_DMASYNC_POSTWRITE); |
| 3626 | bus_dmamap_unload(txq->ift_tso_buf_tag, |
| 3627 | txq->ift_sds.ifsd_tso_map[cidx]); |
| 3628 | } else { |
| 3629 | bus_dmamap_sync(txq->ift_buf_tag, |
| 3630 | txq->ift_sds.ifsd_map[cidx], |
| 3631 | BUS_DMASYNC_POSTWRITE); |
| 3632 | bus_dmamap_unload(txq->ift_buf_tag, |
| 3633 | txq->ift_sds.ifsd_map[cidx]); |
| 3634 | } |
| 3635 | /* XXX we don't support any drivers that batch packets yet */ |
| 3636 | MPASS(m->m_nextpkt == NULL); |
| 3637 | m_freem(m); |
| 3638 | ifsd_m[cidx] = NULL; |
| 3639 | #if MEMORY_LOGGING |
| 3640 | txq->ift_dequeued++; |
| 3641 | #endif |
| 3642 | DBG_COUNTER_INC(tx_frees); |
| 3643 | } |
| 3644 | if (__predict_false(++cidx == qsize)) { |
| 3645 | cidx = 0; |
| 3646 | gen = 0; |
| 3647 | } |
| 3648 | } |
| 3649 | txq->ift_cidx = cidx; |
| 3650 | txq->ift_gen = gen; |
| 3651 | } |
| 3652 | |
| 3653 | static __inline int |
| 3654 | iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) |
no test coverage detected