| 330 | } |
| 331 | |
| 332 | static int |
| 333 | clock_attach(device_t dev) |
| 334 | { |
| 335 | struct clock_softc *sc; |
| 336 | |
| 337 | if (device_get_unit(dev) != 0) |
| 338 | panic("can't attach more clocks"); |
| 339 | |
| 340 | softc = sc = device_get_softc(dev); |
| 341 | cpu_establish_hardintr("compare", clock_intr, NULL, |
| 342 | sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler); |
| 343 | |
| 344 | sc->tc.tc_get_timecount = counter_get_timecount; |
| 345 | sc->tc.tc_counter_mask = 0xffffffff; |
| 346 | sc->tc.tc_frequency = counter_freq; |
| 347 | sc->tc.tc_name = "MIPS32"; |
| 348 | sc->tc.tc_quality = 800; |
| 349 | sc->tc.tc_priv = sc; |
| 350 | tc_init(&sc->tc); |
| 351 | sc->et.et_name = "MIPS32"; |
| 352 | #if 0 |
| 353 | sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | |
| 354 | ET_FLAGS_PERCPU; |
| 355 | #endif |
| 356 | sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU; |
| 357 | sc->et.et_quality = 800; |
| 358 | sc->et.et_frequency = counter_freq; |
| 359 | sc->et.et_min_period = 0x00004000LLU; /* To be safe. */ |
| 360 | sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; |
| 361 | sc->et.et_start = clock_start; |
| 362 | sc->et.et_stop = clock_stop; |
| 363 | sc->et.et_priv = sc; |
| 364 | et_register(&sc->et); |
| 365 | return (0); |
| 366 | } |
| 367 | |
| 368 | static device_method_t clock_methods[] = { |
| 369 | /* Device interface */ |
nothing calls this directly
no test coverage detected