| 93 | static void tlb_invalidate_one(unsigned); |
| 94 | |
| 95 | void |
| 96 | tlb_insert_wired(unsigned i, vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1) |
| 97 | { |
| 98 | register_t asid; |
| 99 | register_t s; |
| 100 | |
| 101 | va &= ~PAGE_MASK; |
| 102 | |
| 103 | s = intr_disable(); |
| 104 | asid = mips_rd_entryhi() & TLBHI_ASID_MASK; |
| 105 | |
| 106 | mips_wr_index(i); |
| 107 | mips_wr_pagemask(0); |
| 108 | mips_wr_entryhi(TLBHI_ENTRY(va, 0)); |
| 109 | mips_wr_entrylo0(pte0); |
| 110 | mips_wr_entrylo1(pte1); |
| 111 | tlb_write_indexed(); |
| 112 | |
| 113 | mips_wr_entryhi(asid); |
| 114 | intr_restore(s); |
| 115 | } |
| 116 | |
| 117 | void |
| 118 | tlb_invalidate_address(struct pmap *pmap, vm_offset_t va) |
no test coverage detected