| 329 | } |
| 330 | |
| 331 | static int |
| 332 | clock_attach(device_t dev) |
| 333 | { |
| 334 | struct clock_softc *sc; |
| 335 | #ifndef INTRNG |
| 336 | int error; |
| 337 | #endif |
| 338 | |
| 339 | if (device_get_unit(dev) != 0) |
| 340 | panic("can't attach more clocks"); |
| 341 | |
| 342 | softc = sc = device_get_softc(dev); |
| 343 | #ifdef INTRNG |
| 344 | cpu_establish_hardintr("clock", clock_intr, NULL, sc, 5, INTR_TYPE_CLK, |
| 345 | NULL); |
| 346 | #else |
| 347 | sc->intr_rid = 0; |
| 348 | sc->intr_res = bus_alloc_resource(dev, |
| 349 | SYS_RES_IRQ, &sc->intr_rid, 5, 5, 1, RF_ACTIVE); |
| 350 | if (sc->intr_res == NULL) { |
| 351 | device_printf(dev, "failed to allocate irq\n"); |
| 352 | return (ENXIO); |
| 353 | } |
| 354 | error = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, |
| 355 | clock_intr, NULL, sc, &sc->intr_handler); |
| 356 | if (error != 0) { |
| 357 | device_printf(dev, "bus_setup_intr returned %d\n", error); |
| 358 | return (error); |
| 359 | } |
| 360 | #endif |
| 361 | |
| 362 | sc->tc.tc_get_timecount = counter_get_timecount; |
| 363 | sc->tc.tc_counter_mask = 0xffffffff; |
| 364 | sc->tc.tc_frequency = counter_freq; |
| 365 | sc->tc.tc_name = "MIPS32"; |
| 366 | sc->tc.tc_quality = 800; |
| 367 | sc->tc.tc_priv = sc; |
| 368 | tc_init(&sc->tc); |
| 369 | sc->et.et_name = "MIPS32"; |
| 370 | sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | |
| 371 | ET_FLAGS_PERCPU; |
| 372 | sc->et.et_quality = 800; |
| 373 | sc->et.et_frequency = counter_freq; |
| 374 | sc->et.et_min_period = 0x00004000LLU; /* To be safe. */ |
| 375 | sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; |
| 376 | sc->et.et_start = clock_start; |
| 377 | sc->et.et_stop = clock_stop; |
| 378 | sc->et.et_priv = sc; |
| 379 | et_register(&sc->et); |
| 380 | return (0); |
| 381 | } |
| 382 | |
| 383 | static device_method_t clock_methods[] = { |
| 384 | /* Device interface */ |
nothing calls this directly
no test coverage detected