| 1200 | } |
| 1201 | |
| 1202 | static void |
| 1203 | mtk_pcie_phy_setup_slots(device_t dev) |
| 1204 | { |
| 1205 | struct mtk_pci_softc *sc = device_get_softc(dev); |
| 1206 | uint32_t bar0_val, val; |
| 1207 | int i; |
| 1208 | |
| 1209 | /* Disable all PCIe interrupts */ |
| 1210 | MT_WRITE32(sc, MTK_PCI_PCIENA, 0); |
| 1211 | |
| 1212 | /* Default bar0_val is 64M, enabled */ |
| 1213 | bar0_val = 0x03FF0001; |
| 1214 | |
| 1215 | /* But we override it to 2G, enabled for some SoCs */ |
| 1216 | if (sc->socid == MTK_SOC_MT7620A || sc->socid == MTK_SOC_MT7628 || |
| 1217 | sc->socid == MTK_SOC_MT7688 || sc->socid == MTK_SOC_MT7621) |
| 1218 | bar0_val = 0x7FFF0001; |
| 1219 | |
| 1220 | /* We still don't know which slots have linked up */ |
| 1221 | sc->pcie_link_status = 0; |
| 1222 | |
| 1223 | /* XXX: I am not sure if this delay is really necessary */ |
| 1224 | DELAY(500000); |
| 1225 | |
| 1226 | /* |
| 1227 | * See which slots have links and mark them. |
| 1228 | * Set up all slots' BARs and make them look like PCIe bridges. |
| 1229 | */ |
| 1230 | for (i = 0; i < sc->num_slots; i++) { |
| 1231 | /* If slot has link - mark it */ |
| 1232 | if (MT_READ32(sc, MTK_PCIE_STATUS(i)) & 1) |
| 1233 | sc->pcie_link_status |= (1<<i); |
| 1234 | else |
| 1235 | continue; |
| 1236 | |
| 1237 | /* Generic slot configuration follows */ |
| 1238 | |
| 1239 | /* We enable BAR0 */ |
| 1240 | MT_WRITE32(sc, MTK_PCIE_BAR0SETUP(i), bar0_val); |
| 1241 | /* and disable BAR1 */ |
| 1242 | MT_WRITE32(sc, MTK_PCIE_BAR1SETUP(i), 0); |
| 1243 | /* Internal memory base has no offset */ |
| 1244 | MT_WRITE32(sc, MTK_PCIE_IMBASEBAR0(i), 0); |
| 1245 | /* We're a PCIe bridge */ |
| 1246 | MT_WRITE32(sc, MTK_PCIE_CLASS(i), 0x06040001); |
| 1247 | |
| 1248 | val = mtk_pci_read_config(dev, 0, i, 0, 0x4, 4); |
| 1249 | mtk_pci_write_config(dev, 0, i, 0, 0x4, val | 0x4, 4); |
| 1250 | val = mtk_pci_read_config(dev, 0, i, 0, 0x70c, 4); |
| 1251 | val &= ~(0xff << 8); |
| 1252 | val |= (0x50 << 8); |
| 1253 | mtk_pci_write_config(dev, 0, i, 0, 0x70c, val, 4); |
| 1254 | |
| 1255 | mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEL_1, 0xff, 1); |
| 1256 | mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEH_1, 0xffff, 2); |
| 1257 | mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITL_1, 0, 1); |
| 1258 | mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITH_1, 0, 2); |
| 1259 | mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMBASE_1, 0xffff, 2); |
no test coverage detected