| 999 | } |
| 1000 | |
| 1001 | static void |
| 1002 | mtk_pcie_phy_mt7628_setup(struct mtk_pci_softc *sc, uint32_t off) |
| 1003 | { |
| 1004 | uint32_t xtal_sel; |
| 1005 | |
| 1006 | xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6; |
| 1007 | xtal_sel &= 0x1; |
| 1008 | |
| 1009 | mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1); |
| 1010 | mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0); |
| 1011 | mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1); |
| 1012 | mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0); |
| 1013 | mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 3); |
| 1014 | |
| 1015 | if (xtal_sel == 1) { |
| 1016 | mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x7d); |
| 1017 | mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x08); |
| 1018 | mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x01); |
| 1019 | mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x1f400000); |
| 1020 | mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x013d); |
| 1021 | mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x74); |
| 1022 | mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x74); |
| 1023 | } else { |
| 1024 | mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x64); |
| 1025 | mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x0a); |
| 1026 | mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x00); |
| 1027 | mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x19000000); |
| 1028 | mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x018d); |
| 1029 | mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x4a); |
| 1030 | mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x4a); |
| 1031 | } |
| 1032 | |
| 1033 | mtk_pcie_phy_set(sc, off + 0x498, 0, 8, 5); |
| 1034 | mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1); |
| 1035 | mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0); |
| 1036 | } |
| 1037 | |
| 1038 | static int |
| 1039 | mtk_pcie_phy_mt7628_init(device_t dev) |
no test coverage detected