| 1105 | } |
| 1106 | |
| 1107 | static int |
| 1108 | mtk_pcie_phy_mt7620_init(device_t dev) |
| 1109 | { |
| 1110 | struct mtk_pci_softc *sc = device_get_softc(dev); |
| 1111 | |
| 1112 | /* |
| 1113 | * The below sets the PCIe PHY to bypass the PCIe DLL and enables |
| 1114 | * "elastic buffer control", whatever that may be... |
| 1115 | */ |
| 1116 | if (mtk_pcie_phy_mt7620_set(sc, 0x00, 0x80) || |
| 1117 | mtk_pcie_phy_mt7620_set(sc, 0x01, 0x04) || |
| 1118 | mtk_pcie_phy_mt7620_set(sc, 0x68, 0x84)) |
| 1119 | return (ENXIO); |
| 1120 | |
| 1121 | /* Stop PCIe */ |
| 1122 | if (mtk_pcie_phy_stop(dev)) |
| 1123 | return (ENXIO); |
| 1124 | |
| 1125 | /* Restore PPLL to a sane state before going on */ |
| 1126 | mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVPD, PDRV_SW_SET); |
| 1127 | |
| 1128 | /* No PCIe on the MT7620N */ |
| 1129 | if (!(mtk_sysctl_get(SYSCTL_REVID) & MT7620_PKG_BGA)) { |
| 1130 | device_printf(dev, "PCIe disabled for MT7620N\n"); |
| 1131 | mtk_sysctl_clr_set(MT7620_PPLL_CFG0, 0, PPLL_SW_SET); |
| 1132 | mtk_sysctl_clr_set(MT7620_PPLL_CFG1, 0, PPLL_PD); |
| 1133 | return (ENXIO); |
| 1134 | } |
| 1135 | |
| 1136 | /* PCIe device reset pin is in normal mode */ |
| 1137 | mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7620_PERST_GPIO_MODE, |
| 1138 | MT7620_PERST); |
| 1139 | |
| 1140 | /* Enable PCIe now */ |
| 1141 | if (mtk_pcie_phy_start(dev)) |
| 1142 | return (ENXIO); |
| 1143 | |
| 1144 | /* Give it a chance to sink in */ |
| 1145 | DELAY(100000); |
| 1146 | |
| 1147 | /* If PLL is not locked - bail */ |
| 1148 | if (!(mtk_sysctl_get(MT7620_PPLL_CFG1) & PPLL_LOCKED)) { |
| 1149 | device_printf(dev, "no PPLL not lock\n"); |
| 1150 | mtk_pcie_phy_stop(dev); |
| 1151 | return (ENXIO); |
| 1152 | } |
| 1153 | |
| 1154 | /* Configure PCIe PLL */ |
| 1155 | mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVOHZ | LC_CKDRVHZ, |
| 1156 | LC_CKDRVPD | PDRV_SW_SET); |
| 1157 | |
| 1158 | /* and give it a chance to settle */ |
| 1159 | DELAY(100000); |
| 1160 | |
| 1161 | /* Deassert PCIe device reset */ |
| 1162 | MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0); |
| 1163 | |
| 1164 | /* MT7620 supports one PCIe slot */ |
no test coverage detected