| 549 | } |
| 550 | |
| 551 | static unsigned |
| 552 | octopci_init_device(device_t dev, unsigned b, unsigned s, unsigned f, unsigned secbus) |
| 553 | { |
| 554 | unsigned barnum, bars; |
| 555 | uint8_t brctl; |
| 556 | uint8_t class, subclass; |
| 557 | uint8_t command; |
| 558 | uint8_t hdrtype; |
| 559 | |
| 560 | /* Read header type (again.) */ |
| 561 | hdrtype = octopci_read_config(dev, b, s, f, PCIR_HDRTYPE, 1); |
| 562 | |
| 563 | /* |
| 564 | * Disable memory and I/O while programming BARs. |
| 565 | */ |
| 566 | command = octopci_read_config(dev, b, s, f, PCIR_COMMAND, 1); |
| 567 | command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); |
| 568 | octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1); |
| 569 | |
| 570 | DELAY(10000); |
| 571 | |
| 572 | /* Program BARs. */ |
| 573 | switch (hdrtype & PCIM_HDRTYPE) { |
| 574 | case PCIM_HDRTYPE_NORMAL: |
| 575 | bars = 6; |
| 576 | break; |
| 577 | case PCIM_HDRTYPE_BRIDGE: |
| 578 | bars = 2; |
| 579 | break; |
| 580 | case PCIM_HDRTYPE_CARDBUS: |
| 581 | bars = 0; |
| 582 | break; |
| 583 | default: |
| 584 | device_printf(dev, "%02x.%02x:%02x: invalid header type %#x\n", |
| 585 | b, s, f, hdrtype); |
| 586 | return (secbus); |
| 587 | } |
| 588 | |
| 589 | barnum = 0; |
| 590 | while (barnum < bars) |
| 591 | barnum = octopci_init_bar(dev, b, s, f, barnum, &command); |
| 592 | |
| 593 | /* Enable bus mastering. */ |
| 594 | command |= PCIM_CMD_BUSMASTEREN; |
| 595 | |
| 596 | /* Enable whatever facilities the BARs require. */ |
| 597 | octopci_write_config(dev, b, s, f, PCIR_COMMAND, command, 1); |
| 598 | |
| 599 | DELAY(10000); |
| 600 | |
| 601 | /* |
| 602 | * Set cache line size. On Octeon it should be 128 bytes, |
| 603 | * but according to Linux some Intel bridges have trouble |
| 604 | * with values over 64 bytes, so use 64 bytes. |
| 605 | */ |
| 606 | octopci_write_config(dev, b, s, f, PCIR_CACHELNSZ, 16, 1); |
| 607 | |
| 608 | /* Set latency timer. */ |
no test coverage detected