| 530 | } |
| 531 | |
| 532 | void |
| 533 | platform_reset(void) |
| 534 | { |
| 535 | struct bcm_platform *bp; |
| 536 | bool bcm4785war; |
| 537 | |
| 538 | printf("bcm::platform_reset()\n"); |
| 539 | intr_disable(); |
| 540 | |
| 541 | #ifdef CFE |
| 542 | /* Fall back on CFE if reset requested during platform |
| 543 | * data initialization */ |
| 544 | if (!bcm_platform_data_avail) { |
| 545 | cfe_exit(0, 0); |
| 546 | while (1); |
| 547 | } |
| 548 | #endif |
| 549 | |
| 550 | bp = bcm_get_platform(); |
| 551 | bcm4785war = false; |
| 552 | |
| 553 | /* Handle BCM4785-specific behavior */ |
| 554 | if (bp->cid.chip_id == BHND_CHIPID_BCM4785) { |
| 555 | bcm4785war = true; |
| 556 | |
| 557 | /* Switch to async mode */ |
| 558 | bcm_bmips_wr_pllcfg3(BMIPS_BCMCFG_PLLCFG3_SM); |
| 559 | } |
| 560 | |
| 561 | /* Set watchdog (PMU or ChipCommon) */ |
| 562 | if (bp->pmu_addr != 0x0) { |
| 563 | BCM_PMU_WRITE_4(bp, BHND_PMU_WATCHDOG, 1); |
| 564 | } else |
| 565 | BCM_CHIPC_WRITE_4(bp, CHIPC_WATCHDOG, 1); |
| 566 | |
| 567 | /* BCM4785 */ |
| 568 | if (bcm4785war) { |
| 569 | mips_sync(); |
| 570 | __asm __volatile("wait"); |
| 571 | } |
| 572 | |
| 573 | while (1); |
| 574 | } |
| 575 | |
| 576 | void |
| 577 | platform_start(__register_t a0, __register_t a1, __register_t a2, |
nothing calls this directly
no test coverage detected