| 2583 | } |
| 2584 | |
| 2585 | static void |
| 2586 | arge_intr(void *arg) |
| 2587 | { |
| 2588 | struct arge_softc *sc = arg; |
| 2589 | uint32_t status; |
| 2590 | struct ifnet *ifp = sc->arge_ifp; |
| 2591 | #ifdef ARGE_DEBUG |
| 2592 | int i; |
| 2593 | #endif |
| 2594 | |
| 2595 | status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); |
| 2596 | status |= sc->arge_intr_status; |
| 2597 | |
| 2598 | ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status, |
| 2599 | "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD" |
| 2600 | "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); |
| 2601 | |
| 2602 | /* |
| 2603 | * Is it our interrupt at all? |
| 2604 | */ |
| 2605 | if (status == 0) { |
| 2606 | sc->stats.intr_stray2++; |
| 2607 | return; |
| 2608 | } |
| 2609 | |
| 2610 | #ifdef ARGE_DEBUG |
| 2611 | for (i = 0; i < 32; i++) { |
| 2612 | if (status & (1U << i)) { |
| 2613 | sc->intr_stats.count[i]++; |
| 2614 | } |
| 2615 | } |
| 2616 | #endif |
| 2617 | |
| 2618 | if (status & DMA_INTR_RX_BUS_ERROR) { |
| 2619 | ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR); |
| 2620 | device_printf(sc->arge_dev, "RX bus error"); |
| 2621 | return; |
| 2622 | } |
| 2623 | |
| 2624 | if (status & DMA_INTR_TX_BUS_ERROR) { |
| 2625 | ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR); |
| 2626 | device_printf(sc->arge_dev, "TX bus error"); |
| 2627 | return; |
| 2628 | } |
| 2629 | |
| 2630 | ARGE_LOCK(sc); |
| 2631 | arge_flush_ddr(sc); |
| 2632 | |
| 2633 | if (status & DMA_INTR_RX_PKT_RCVD) |
| 2634 | arge_rx_locked(sc); |
| 2635 | |
| 2636 | /* |
| 2637 | * RX overrun disables the receiver. |
| 2638 | * Clear indication and re-enable rx. |
| 2639 | */ |
| 2640 | if ( status & DMA_INTR_RX_OVERFLOW) { |
| 2641 | ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW); |
| 2642 | ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); |
nothing calls this directly
no test coverage detected