* Send an IPI forcing a sequentially consistent fence. * * Allows replacement of an explicitly fence with a compiler barrier. * Trades speed up during normal execution for a significant slowdown when * the barrier is needed. */
| 1036 | * the barrier is needed. |
| 1037 | */ |
| 1038 | void |
| 1039 | cpus_fence_seq_cst(void) |
| 1040 | { |
| 1041 | |
| 1042 | #ifdef SMP |
| 1043 | smp_rendezvous( |
| 1044 | smp_no_rendezvous_barrier, |
| 1045 | cpus_fence_seq_cst_issue, |
| 1046 | smp_no_rendezvous_barrier, |
| 1047 | NULL |
| 1048 | ); |
| 1049 | #else |
| 1050 | cpus_fence_seq_cst_issue(NULL); |
| 1051 | #endif |
| 1052 | } |
| 1053 | |
| 1054 | /* Extra care is taken with this sysctl because the data type is volatile */ |
| 1055 | static int |
no test coverage detected