* NB: The sequence of updating a page table followed by accesses to the * corresponding pages is subject to the situation described in the "AMD64 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23, * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG * right after modifying the PTE bits is crucial. */
| 1554 | * right after modifying the PTE bits is crucial. |
| 1555 | */ |
| 1556 | static __inline void |
| 1557 | invlcaddr(void *caddr) |
| 1558 | { |
| 1559 | |
| 1560 | invlpg((u_int)caddr); |
| 1561 | } |
| 1562 | |
| 1563 | /* |
| 1564 | * Super fast pmap_pte routine best used when scanning |
no test coverage detected