| 1206 | } |
| 1207 | |
| 1208 | void |
| 1209 | cpu_setregs(void) |
| 1210 | { |
| 1211 | unsigned int cr0; |
| 1212 | |
| 1213 | cr0 = rcr0(); |
| 1214 | |
| 1215 | /* |
| 1216 | * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support: |
| 1217 | * |
| 1218 | * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT |
| 1219 | * instructions. We must set the CR0_MP bit and use the CR0_TS |
| 1220 | * bit to control the trap, because setting the CR0_EM bit does |
| 1221 | * not cause WAIT instructions to trap. It's important to trap |
| 1222 | * WAIT instructions - otherwise the "wait" variants of no-wait |
| 1223 | * control instructions would degenerate to the "no-wait" variants |
| 1224 | * after FP context switches but work correctly otherwise. It's |
| 1225 | * particularly important to trap WAITs when there is no NPX - |
| 1226 | * otherwise the "wait" variants would always degenerate. |
| 1227 | * |
| 1228 | * Try setting CR0_NE to get correct error reporting on 486DX's. |
| 1229 | * Setting it should fail or do nothing on lesser processors. |
| 1230 | */ |
| 1231 | cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; |
| 1232 | load_cr0(cr0); |
| 1233 | load_gs(_udatasel); |
| 1234 | } |
| 1235 | |
| 1236 | u_long bootdev; /* not a struct cdev *- encoding is different */ |
| 1237 | SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev, |
no test coverage detected