| 8374 | } |
| 8375 | |
| 8376 | static void |
| 8377 | spa_sync_aux_dev(spa_t *spa, spa_aux_vdev_t *sav, dmu_tx_t *tx, |
| 8378 | const char *config, const char *entry) |
| 8379 | { |
| 8380 | nvlist_t *nvroot; |
| 8381 | nvlist_t **list; |
| 8382 | int i; |
| 8383 | |
| 8384 | if (!sav->sav_sync) |
| 8385 | return; |
| 8386 | |
| 8387 | /* |
| 8388 | * Update the MOS nvlist describing the list of available devices. |
| 8389 | * spa_validate_aux() will have already made sure this nvlist is |
| 8390 | * valid and the vdevs are labeled appropriately. |
| 8391 | */ |
| 8392 | if (sav->sav_object == 0) { |
| 8393 | sav->sav_object = dmu_object_alloc(spa->spa_meta_objset, |
| 8394 | DMU_OT_PACKED_NVLIST, 1 << 14, DMU_OT_PACKED_NVLIST_SIZE, |
| 8395 | sizeof (uint64_t), tx); |
| 8396 | VERIFY(zap_update(spa->spa_meta_objset, |
| 8397 | DMU_POOL_DIRECTORY_OBJECT, entry, sizeof (uint64_t), 1, |
| 8398 | &sav->sav_object, tx) == 0); |
| 8399 | } |
| 8400 | |
| 8401 | VERIFY(nvlist_alloc(&nvroot, NV_UNIQUE_NAME, KM_SLEEP) == 0); |
| 8402 | if (sav->sav_count == 0) { |
| 8403 | VERIFY(nvlist_add_nvlist_array(nvroot, config, NULL, 0) == 0); |
| 8404 | } else { |
| 8405 | list = kmem_alloc(sav->sav_count*sizeof (void *), KM_SLEEP); |
| 8406 | for (i = 0; i < sav->sav_count; i++) |
| 8407 | list[i] = vdev_config_generate(spa, sav->sav_vdevs[i], |
| 8408 | B_FALSE, VDEV_CONFIG_L2CACHE); |
| 8409 | VERIFY(nvlist_add_nvlist_array(nvroot, config, list, |
| 8410 | sav->sav_count) == 0); |
| 8411 | for (i = 0; i < sav->sav_count; i++) |
| 8412 | nvlist_free(list[i]); |
| 8413 | kmem_free(list, sav->sav_count * sizeof (void *)); |
| 8414 | } |
| 8415 | |
| 8416 | spa_sync_nvlist(spa, sav->sav_object, nvroot, tx); |
| 8417 | nvlist_free(nvroot); |
| 8418 | |
| 8419 | sav->sav_sync = B_FALSE; |
| 8420 | } |
| 8421 | |
| 8422 | /* |
| 8423 | * Rebuild spa's all-vdev ZAP from the vdev ZAPs indicated in each vdev_t. |
no test coverage detected