Clear previous configuration of the PL by asserting PROG_B. */
| 423 | |
| 424 | /* Clear previous configuration of the PL by asserting PROG_B. */ |
| 425 | static int |
| 426 | zy7_devcfg_reset_pl(struct zy7_devcfg_softc *sc) |
| 427 | { |
| 428 | uint32_t devcfg_ctl; |
| 429 | int tries, err; |
| 430 | |
| 431 | DEVCFG_SC_ASSERT_LOCKED(sc); |
| 432 | |
| 433 | devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL); |
| 434 | |
| 435 | /* Clear sticky bits and set up INIT signal positive edge interrupt. */ |
| 436 | WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); |
| 437 | WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); |
| 438 | |
| 439 | /* Deassert PROG_B (active low). */ |
| 440 | devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; |
| 441 | WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); |
| 442 | |
| 443 | /* |
| 444 | * Wait for INIT to assert. If it is already asserted, we may not get |
| 445 | * an edge interrupt so cancel it and continue. |
| 446 | */ |
| 447 | if ((RD4(sc, ZY7_DEVCFG_STATUS) & |
| 448 | ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) { |
| 449 | /* Already asserted. Cancel interrupt. */ |
| 450 | WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); |
| 451 | } |
| 452 | else { |
| 453 | /* Wait for positive edge interrupt. */ |
| 454 | err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz); |
| 455 | if (err != 0) |
| 456 | return (err); |
| 457 | } |
| 458 | |
| 459 | /* Reassert PROG_B (active low). */ |
| 460 | devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B; |
| 461 | WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); |
| 462 | |
| 463 | /* Wait for INIT deasserted. This happens almost instantly. */ |
| 464 | tries = 0; |
| 465 | while ((RD4(sc, ZY7_DEVCFG_STATUS) & |
| 466 | ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) { |
| 467 | if (++tries >= 100) |
| 468 | return (EIO); |
| 469 | DELAY(5); |
| 470 | } |
| 471 | |
| 472 | /* Clear sticky bits and set up INIT positive edge interrupt. */ |
| 473 | WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); |
| 474 | WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); |
| 475 | |
| 476 | /* Deassert PROG_B again. */ |
| 477 | devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; |
| 478 | WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); |
| 479 | |
| 480 | /* |
| 481 | * Wait for INIT asserted indicating FPGA internal initialization |
| 482 | * is complete. |
no test coverage detected