| 353 | } |
| 354 | |
| 355 | static int |
| 356 | zy7_devcfg_init_fclk_sysctl(struct zy7_devcfg_softc *sc) |
| 357 | { |
| 358 | struct sysctl_oid *fclk_node; |
| 359 | char fclk_num[4]; |
| 360 | int i; |
| 361 | |
| 362 | sysctl_ctx_init(&sc->sysctl_tree); |
| 363 | sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree, |
| 364 | SYSCTL_STATIC_CHILDREN(_hw_fpga), OID_AUTO, "fclk", |
| 365 | CTLFLAG_RD | CTLFLAG_MPSAFE, 0, ""); |
| 366 | if (sc->sysctl_tree_top == NULL) { |
| 367 | sysctl_ctx_free(&sc->sysctl_tree); |
| 368 | return (-1); |
| 369 | } |
| 370 | |
| 371 | for (i = 0; i < FCLK_NUM; i++) { |
| 372 | snprintf(fclk_num, sizeof(fclk_num), "%d", i); |
| 373 | fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree, |
| 374 | SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num, |
| 375 | CTLFLAG_RD | CTLFLAG_MPSAFE, 0, ""); |
| 376 | |
| 377 | SYSCTL_ADD_INT(&sc->sysctl_tree, |
| 378 | SYSCTL_CHILDREN(fclk_node), OID_AUTO, |
| 379 | "actual_freq", CTLFLAG_RD, |
| 380 | &fclk_configs[i].actual_frequency, i, |
| 381 | "Actual frequency"); |
| 382 | SYSCTL_ADD_PROC(&sc->sysctl_tree, |
| 383 | SYSCTL_CHILDREN(fclk_node), OID_AUTO, |
| 384 | "freq", CTLFLAG_RW | CTLTYPE_INT | CTLFLAG_NEEDGIANT, |
| 385 | &fclk_configs[i], i, |
| 386 | zy7_devcfg_fclk_sysctl_freq, |
| 387 | "I", "Configured frequency"); |
| 388 | SYSCTL_ADD_PROC(&sc->sysctl_tree, |
| 389 | SYSCTL_CHILDREN(fclk_node), OID_AUTO, |
| 390 | "source", CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, |
| 391 | &fclk_configs[i], i, |
| 392 | zy7_devcfg_fclk_sysctl_source, |
| 393 | "A", "Clock source"); |
| 394 | } |
| 395 | |
| 396 | return (0); |
| 397 | } |
| 398 | |
| 399 | /* Enable programming the PL through PCAP. */ |
| 400 | static void |
no test coverage detected