| 132 | } |
| 133 | |
| 134 | static int |
| 135 | omap_uhh_init(struct omap_uhh_softc *isc) |
| 136 | { |
| 137 | uint8_t tll_ch_mask; |
| 138 | uint32_t reg; |
| 139 | int i; |
| 140 | |
| 141 | /* Enable Clocks for high speed USBHOST */ |
| 142 | ti_sysc_clock_enable(device_get_parent(isc->sc_dev)); |
| 143 | |
| 144 | /* Read the UHH revision */ |
| 145 | isc->uhh_rev = omap_uhh_read_4(isc, OMAP_USBHOST_UHH_REVISION); |
| 146 | device_printf(isc->sc_dev, "UHH revision 0x%08x\n", isc->uhh_rev); |
| 147 | |
| 148 | /* FIXME */ |
| 149 | #if 0 |
| 150 | if (isc->uhh_rev == OMAP_UHH_REV2) { |
| 151 | /* For OMAP44xx devices you have to enable the per-port clocks: |
| 152 | * PHY_MODE - External ULPI clock |
| 153 | * TTL_MODE - Internal UTMI clock |
| 154 | * HSIC_MODE - Internal 480Mhz and 60Mhz clocks |
| 155 | */ |
| 156 | switch(isc->port_mode[0]) { |
| 157 | case EHCI_HCD_OMAP_MODE_UNKNOWN: |
| 158 | break; |
| 159 | case EHCI_HCD_OMAP_MODE_PHY: |
| 160 | if (ti_prcm_clk_set_source(USBP1_PHY_CLK, EXT_CLK)) |
| 161 | device_printf(isc->sc_dev, |
| 162 | "failed to set clock source for port 0\n"); |
| 163 | if (ti_prcm_clk_enable(USBP1_PHY_CLK)) |
| 164 | device_printf(isc->sc_dev, |
| 165 | "failed to set clock USBP1_PHY_CLK source for port 0\n"); |
| 166 | break; |
| 167 | case EHCI_HCD_OMAP_MODE_TLL: |
| 168 | if (ti_prcm_clk_enable(USBP1_UTMI_CLK)) |
| 169 | device_printf(isc->sc_dev, |
| 170 | "failed to set clock USBP1_PHY_CLK source for port 0\n"); |
| 171 | break; |
| 172 | case EHCI_HCD_OMAP_MODE_HSIC: |
| 173 | if (ti_prcm_clk_enable(USBP1_HSIC_CLK)) |
| 174 | device_printf(isc->sc_dev, |
| 175 | "failed to set clock USBP1_PHY_CLK source for port 0\n"); |
| 176 | break; |
| 177 | default: |
| 178 | device_printf(isc->sc_dev, "unknown port mode %d for port 0\n", isc->port_mode[0]); |
| 179 | } |
| 180 | switch(isc->port_mode[1]) { |
| 181 | case EHCI_HCD_OMAP_MODE_UNKNOWN: |
| 182 | break; |
| 183 | case EHCI_HCD_OMAP_MODE_PHY: |
| 184 | if (ti_prcm_clk_set_source(USBP2_PHY_CLK, EXT_CLK)) |
| 185 | device_printf(isc->sc_dev, |
| 186 | "failed to set clock source for port 0\n"); |
| 187 | if (ti_prcm_clk_enable(USBP2_PHY_CLK)) |
| 188 | device_printf(isc->sc_dev, |
| 189 | "failed to set clock USBP2_PHY_CLK source for port 1\n"); |
| 190 | break; |
| 191 | case EHCI_HCD_OMAP_MODE_TLL: |
no test coverage detected