* ti_sdma_stop_xfer - stops any currently active transfers * @ch: the channel number to set the endianness of * * This function call is effectively a NOP if no transaction is in progress. * * LOCKING: * DMA registers protected by internal mutex * * RETURNS: * EH_HANDLED or EH_NOT_HANDLED */
| 797 | * EH_HANDLED or EH_NOT_HANDLED |
| 798 | */ |
| 799 | int |
| 800 | ti_sdma_stop_xfer(unsigned int ch) |
| 801 | { |
| 802 | struct ti_sdma_softc *sc = ti_sdma_sc; |
| 803 | unsigned int j; |
| 804 | |
| 805 | /* Sanity check */ |
| 806 | if (sc == NULL) |
| 807 | return (ENOMEM); |
| 808 | |
| 809 | TI_SDMA_LOCK(sc); |
| 810 | |
| 811 | if ((sc->sc_active_channels & (1 << ch)) == 0) { |
| 812 | TI_SDMA_UNLOCK(sc); |
| 813 | return (EINVAL); |
| 814 | } |
| 815 | |
| 816 | /* Disable all DMA interrupts for the channel. */ |
| 817 | ti_sdma_write_4(sc, DMA4_CICR(ch), 0); |
| 818 | |
| 819 | /* Make sure the DMA transfer is stopped. */ |
| 820 | ti_sdma_write_4(sc, DMA4_CCR(ch), 0); |
| 821 | |
| 822 | /* Clear the CSR register and IRQ status register */ |
| 823 | ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK); |
| 824 | for (j = 0; j < NUM_DMA_IRQS; j++) { |
| 825 | ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch)); |
| 826 | } |
| 827 | |
| 828 | /* Configuration registers need to be re-written on the next xfer */ |
| 829 | sc->sc_channel[ch].need_reg_write = 1; |
| 830 | |
| 831 | TI_SDMA_UNLOCK(sc); |
| 832 | |
| 833 | return (0); |
| 834 | } |
| 835 | |
| 836 | /** |
| 837 | * ti_sdma_set_xfer_endianess - sets the endianness of subsequent transfers |
nothing calls this directly
no test coverage detected