* ti_sdma_start_xfer - starts a DMA transfer * @ch: the channel number to set the endianness of * @src_paddr: the source phsyical address * @dst_paddr: the destination phsyical address * @frmcnt: the number of frames per block * @elmcnt: the number of elements in a frame, an element is either an 8, 16 * or 32-bit value as defined by ti_sdma_set_xfer_burst() * * * LOCKING: * DMA
| 622 | * EH_HANDLED or EH_NOT_HANDLED |
| 623 | */ |
| 624 | int |
| 625 | ti_sdma_start_xfer(unsigned int ch, unsigned int src_paddr, |
| 626 | unsigned long dst_paddr, |
| 627 | unsigned int frmcnt, unsigned int elmcnt) |
| 628 | { |
| 629 | struct ti_sdma_softc *sc = ti_sdma_sc; |
| 630 | struct ti_sdma_channel *channel; |
| 631 | uint32_t ccr; |
| 632 | |
| 633 | /* Sanity check */ |
| 634 | if (sc == NULL) |
| 635 | return (ENOMEM); |
| 636 | |
| 637 | TI_SDMA_LOCK(sc); |
| 638 | |
| 639 | if ((sc->sc_active_channels & (1 << ch)) == 0) { |
| 640 | TI_SDMA_UNLOCK(sc); |
| 641 | return (EINVAL); |
| 642 | } |
| 643 | |
| 644 | channel = &sc->sc_channel[ch]; |
| 645 | |
| 646 | /* a) Write the CSDP register */ |
| 647 | ti_sdma_write_4(sc, DMA4_CSDP(ch), |
| 648 | channel->reg_csdp | DMA4_CSDP_WRITE_MODE(1)); |
| 649 | |
| 650 | /* b) Set the number of element per frame CEN[23:0] */ |
| 651 | ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt); |
| 652 | |
| 653 | /* c) Set the number of frame per block CFN[15:0] */ |
| 654 | ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt); |
| 655 | |
| 656 | /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0] */ |
| 657 | ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr); |
| 658 | ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr); |
| 659 | |
| 660 | /* e) Write the CCR register */ |
| 661 | ti_sdma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr); |
| 662 | |
| 663 | /* f) - Set the source element index increment CSEI[15:0] */ |
| 664 | ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001); |
| 665 | |
| 666 | /* - Set the source frame index increment CSFI[15:0] */ |
| 667 | ti_sdma_write_4(sc, DMA4_CSF(ch), 0x0001); |
| 668 | |
| 669 | /* - Set the destination element index increment CDEI[15:0]*/ |
| 670 | ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001); |
| 671 | |
| 672 | /* - Set the destination frame index increment CDFI[31:0] */ |
| 673 | ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001); |
| 674 | |
| 675 | /* Clear the status register */ |
| 676 | ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE); |
| 677 | |
| 678 | /* Write the start-bit and away we go */ |
| 679 | ccr = ti_sdma_read_4(sc, DMA4_CCR(ch)); |
| 680 | ccr |= (1 << 7); |
| 681 | ti_sdma_write_4(sc, DMA4_CCR(ch), ccr); |
nothing calls this directly
no test coverage detected