* ti_sdma_deactivate_channel - deactivates a channel * @ch: the channel to deactivate * * * * LOCKING: * DMA registers protected by internal mutex * * RETURNS: * EH_HANDLED or EH_NOT_HANDLED */
| 399 | * EH_HANDLED or EH_NOT_HANDLED |
| 400 | */ |
| 401 | int |
| 402 | ti_sdma_deactivate_channel(unsigned int ch) |
| 403 | { |
| 404 | struct ti_sdma_softc *sc = ti_sdma_sc; |
| 405 | unsigned int j; |
| 406 | unsigned int addr; |
| 407 | |
| 408 | /* Sanity check */ |
| 409 | if (sc == NULL) |
| 410 | return (ENOMEM); |
| 411 | |
| 412 | TI_SDMA_LOCK(sc); |
| 413 | |
| 414 | /* First check if the channel is currently active */ |
| 415 | if ((sc->sc_active_channels & (1 << ch)) == 0) { |
| 416 | TI_SDMA_UNLOCK(sc); |
| 417 | return (EBUSY); |
| 418 | } |
| 419 | |
| 420 | /* Mark the channel as inactive */ |
| 421 | sc->sc_active_channels &= ~(1 << ch); |
| 422 | |
| 423 | /* Disable all DMA interrupts for the channel. */ |
| 424 | ti_sdma_write_4(sc, DMA4_CICR(ch), 0); |
| 425 | |
| 426 | /* Make sure the DMA transfer is stopped. */ |
| 427 | ti_sdma_write_4(sc, DMA4_CCR(ch), 0); |
| 428 | |
| 429 | /* Clear the CSR register and IRQ status register */ |
| 430 | ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK); |
| 431 | for (j = 0; j < NUM_DMA_IRQS; j++) { |
| 432 | ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch)); |
| 433 | } |
| 434 | |
| 435 | /* Clear all the channel registers, this should abort any transaction */ |
| 436 | for (addr = DMA4_CCR(ch); addr <= DMA4_COLOR(ch); addr += 4) |
| 437 | ti_sdma_write_4(sc, addr, 0x00000000); |
| 438 | |
| 439 | TI_SDMA_UNLOCK(sc); |
| 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | /** |
| 445 | * ti_sdma_disable_channel_irq - disables IRQ's on the given channel |
nothing calls this directly
no test coverage detected