| 276 | } |
| 277 | |
| 278 | static void |
| 279 | ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, |
| 280 | uint16_t val) |
| 281 | { |
| 282 | struct ti_sdhci_softc *sc = device_get_softc(dev); |
| 283 | uint32_t clkdiv, val32; |
| 284 | |
| 285 | /* |
| 286 | * Translate between the hardware and SDHCI 2.0 or 3.0 representations |
| 287 | * of the clock divisor. See the comments in ti_sdhci_read_2() for |
| 288 | * details. |
| 289 | */ |
| 290 | if (off == SDHCI_CLOCK_CONTROL) { |
| 291 | clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; |
| 292 | if (slot->version >= SDHCI_SPEC_300) |
| 293 | clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & |
| 294 | SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; |
| 295 | clkdiv *= 2; |
| 296 | if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) |
| 297 | clkdiv = MMCHS_SYSCTL_CLKD_MASK; |
| 298 | val32 = RD4(sc, SDHCI_CLOCK_CONTROL); |
| 299 | val32 &= 0xffff0000; |
| 300 | val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << |
| 301 | MMCHS_SYSCTL_CLKD_SHIFT); |
| 302 | val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; |
| 303 | WR4(sc, SDHCI_CLOCK_CONTROL, val32); |
| 304 | return; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * Standard 32-bit handling of command and transfer mode. |
| 309 | */ |
| 310 | if (off == SDHCI_TRANSFER_MODE) { |
| 311 | sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | |
| 312 | ((uint32_t)val & 0x0000ffff); |
| 313 | return; |
| 314 | } else if (off == SDHCI_COMMAND_FLAGS) { |
| 315 | sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | |
| 316 | ((uint32_t)val << 16); |
| 317 | WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); |
| 318 | return; |
| 319 | } |
| 320 | |
| 321 | val32 = RD4(sc, off & ~3); |
| 322 | val32 &= ~(0xffff << (off & 3) * 8); |
| 323 | val32 |= ((val & 0xffff) << (off & 3) * 8); |
| 324 | WR4(sc, off & ~3, val32); |
| 325 | } |
| 326 | |
| 327 | static void |
| 328 | ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, |
nothing calls this directly
no test coverage detected