| 101 | #endif /* EVDEV */ |
| 102 | |
| 103 | static void |
| 104 | ti_adc_enable(struct ti_adc_softc *sc) |
| 105 | { |
| 106 | uint32_t reg; |
| 107 | |
| 108 | TI_ADC_LOCK_ASSERT(sc); |
| 109 | |
| 110 | if (sc->sc_last_state == 1) |
| 111 | return; |
| 112 | |
| 113 | /* Enable the FIFO0 threshold and the end of sequence interrupt. */ |
| 114 | ADC_WRITE4(sc, ADC_IRQENABLE_SET, |
| 115 | ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); |
| 116 | |
| 117 | reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID; |
| 118 | if (sc->sc_tsc_wires > 0) { |
| 119 | reg |= ADC_CTRL_TSC_ENABLE; |
| 120 | switch (sc->sc_tsc_wires) { |
| 121 | case 4: |
| 122 | reg |= ADC_CTRL_TSC_4WIRE; |
| 123 | break; |
| 124 | case 5: |
| 125 | reg |= ADC_CTRL_TSC_5WIRE; |
| 126 | break; |
| 127 | case 8: |
| 128 | reg |= ADC_CTRL_TSC_8WIRE; |
| 129 | break; |
| 130 | default: |
| 131 | break; |
| 132 | } |
| 133 | } |
| 134 | reg |= ADC_CTRL_ENABLE; |
| 135 | /* Enable the ADC. Run thru enabled steps, start the conversions. */ |
| 136 | ADC_WRITE4(sc, ADC_CTRL, reg); |
| 137 | |
| 138 | sc->sc_last_state = 1; |
| 139 | } |
| 140 | |
| 141 | static void |
| 142 | ti_adc_disable(struct ti_adc_softc *sc) |