| 139 | } |
| 140 | |
| 141 | static void |
| 142 | ti_adc_disable(struct ti_adc_softc *sc) |
| 143 | { |
| 144 | int count; |
| 145 | uint32_t data; |
| 146 | |
| 147 | TI_ADC_LOCK_ASSERT(sc); |
| 148 | |
| 149 | if (sc->sc_last_state == 0) |
| 150 | return; |
| 151 | |
| 152 | /* Disable all the enabled steps. */ |
| 153 | ADC_WRITE4(sc, ADC_STEPENABLE, 0); |
| 154 | |
| 155 | /* Disable the ADC. */ |
| 156 | ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE); |
| 157 | |
| 158 | /* Disable the FIFO0 threshold and the end of sequence interrupt. */ |
| 159 | ADC_WRITE4(sc, ADC_IRQENABLE_CLR, |
| 160 | ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); |
| 161 | |
| 162 | /* ACK any pending interrupt. */ |
| 163 | ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS)); |
| 164 | |
| 165 | /* Drain the FIFO data. */ |
| 166 | count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; |
| 167 | while (count > 0) { |
| 168 | data = ADC_READ4(sc, ADC_FIFO0DATA); |
| 169 | count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; |
| 170 | } |
| 171 | |
| 172 | count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; |
| 173 | while (count > 0) { |
| 174 | data = ADC_READ4(sc, ADC_FIFO1DATA); |
| 175 | count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; |
| 176 | } |
| 177 | |
| 178 | sc->sc_last_state = 0; |
| 179 | } |
| 180 | |
| 181 | static int |
| 182 | ti_adc_setup(struct ti_adc_softc *sc) |
no outgoing calls
no test coverage detected