| 857 | } |
| 858 | |
| 859 | static int |
| 860 | init_hw(struct tegra_xhci_softc *sc) |
| 861 | { |
| 862 | int rv; |
| 863 | uint32_t reg; |
| 864 | rman_res_t base_addr; |
| 865 | |
| 866 | base_addr = rman_get_start(sc->xhci_softc.sc_io_res); |
| 867 | |
| 868 | /* Enable FPCI access */ |
| 869 | reg = IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); |
| 870 | reg |= CONFIGURATION_EN_FPCI; |
| 871 | IPFS_WR4(sc, XUSB_HOST_CONFIGURATION, reg); |
| 872 | IPFS_RD4(sc, XUSB_HOST_CONFIGURATION); |
| 873 | |
| 874 | /* Program bar for XHCI base address */ |
| 875 | reg = FPCI_RD4(sc, T_XUSB_CFG_4); |
| 876 | reg &= ~CFG_4_BASE_ADDRESS(~0); |
| 877 | reg |= CFG_4_BASE_ADDRESS((uint32_t)base_addr >> 15); |
| 878 | FPCI_WR4(sc, T_XUSB_CFG_4, reg); |
| 879 | FPCI_WR4(sc, T_XUSB_CFG_5, (uint32_t)((uint64_t)(base_addr) >> 32)); |
| 880 | |
| 881 | /* Enable bus master */ |
| 882 | reg = FPCI_RD4(sc, T_XUSB_CFG_1); |
| 883 | reg |= CFG_1_IO_SPACE; |
| 884 | reg |= CFG_1_MEMORY_SPACE; |
| 885 | reg |= CFG_1_BUS_MASTER; |
| 886 | FPCI_WR4(sc, T_XUSB_CFG_1, reg); |
| 887 | |
| 888 | /* Enable Interrupts */ |
| 889 | reg = IPFS_RD4(sc, XUSB_HOST_INTR_MASK); |
| 890 | reg |= INTR_IP_INT_MASK; |
| 891 | IPFS_WR4(sc, XUSB_HOST_INTR_MASK, reg); |
| 892 | |
| 893 | /* Set hysteresis */ |
| 894 | IPFS_WR4(sc, XUSB_HOST_CLKGATE_HYSTERESIS, 128); |
| 895 | |
| 896 | rv = load_fw(sc); |
| 897 | if (rv != 0) |
| 898 | return rv; |
| 899 | return (0); |
| 900 | } |
| 901 | |
| 902 | static int |
| 903 | tegra_xhci_probe(device_t dev) |
no test coverage detected