| 849 | } |
| 850 | |
| 851 | static int |
| 852 | tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc) |
| 853 | { |
| 854 | int i, rv; |
| 855 | |
| 856 | rv = hwreset_assert(sc->hwreset_pcie_x); |
| 857 | if (rv != 0) { |
| 858 | device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); |
| 859 | return (rv); |
| 860 | } |
| 861 | rv = hwreset_assert(sc->hwreset_afi); |
| 862 | if (rv != 0) { |
| 863 | device_printf(sc->dev, "Cannot assert 'afi' reset\n"); |
| 864 | return (rv); |
| 865 | } |
| 866 | rv = hwreset_assert(sc->hwreset_pex); |
| 867 | if (rv != 0) { |
| 868 | device_printf(sc->dev, "Cannot assert 'pex' reset\n"); |
| 869 | return (rv); |
| 870 | } |
| 871 | |
| 872 | tegra_powergate_power_off(TEGRA_POWERGATE_PCX); |
| 873 | |
| 874 | /* Regulators. */ |
| 875 | for (i = 0; i < nitems(sc->regulators); i++) { |
| 876 | if (sc->regulators[i] == NULL) |
| 877 | continue; |
| 878 | rv = regulator_enable(sc->regulators[i]); |
| 879 | if (rv != 0) { |
| 880 | device_printf(sc->dev, |
| 881 | "Cannot enable '%s' regulator\n", |
| 882 | sc->soc->regulator_names[i]); |
| 883 | return (rv); |
| 884 | } |
| 885 | } |
| 886 | |
| 887 | rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX, |
| 888 | sc->clk_pex, sc->hwreset_pex); |
| 889 | if (rv != 0) { |
| 890 | device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); |
| 891 | return (rv); |
| 892 | } |
| 893 | |
| 894 | rv = hwreset_deassert(sc->hwreset_afi); |
| 895 | if (rv != 0) { |
| 896 | device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); |
| 897 | return (rv); |
| 898 | } |
| 899 | |
| 900 | rv = clk_enable(sc->clk_afi); |
| 901 | if (rv != 0) { |
| 902 | device_printf(sc->dev, "Cannot enable 'afi' clock\n"); |
| 903 | return (rv); |
| 904 | } |
| 905 | if (sc->soc->cml_clk) { |
| 906 | rv = clk_enable(sc->clk_cml); |
| 907 | if (rv != 0) { |
| 908 | device_printf(sc->dev, "Cannot enable 'cml' clock\n"); |
no test coverage detected