| 386 | } |
| 387 | |
| 388 | static void |
| 389 | mv_watchdog_enable_armv5(void) |
| 390 | { |
| 391 | uint32_t val, irq_cause, irq_mask; |
| 392 | |
| 393 | irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); |
| 394 | irq_cause &= timer_softc->config->irq_timer_wd_clr; |
| 395 | write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); |
| 396 | |
| 397 | irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); |
| 398 | irq_mask |= IRQ_TIMER_WD_MASK; |
| 399 | write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); |
| 400 | |
| 401 | val = read_cpu_ctrl(RSTOUTn_MASK); |
| 402 | val |= WD_RST_OUT_EN; |
| 403 | write_cpu_ctrl(RSTOUTn_MASK, val); |
| 404 | |
| 405 | val = mv_get_timer_control(); |
| 406 | val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; |
| 407 | mv_set_timer_control(val); |
| 408 | } |
| 409 | |
| 410 | static void |
| 411 | mv_watchdog_enable_armadaxp(void) |
nothing calls this directly
no test coverage detected