| 408 | } |
| 409 | |
| 410 | static void |
| 411 | mv_watchdog_enable_armadaxp(void) |
| 412 | { |
| 413 | uint32_t irq_cause, val; |
| 414 | |
| 415 | irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); |
| 416 | irq_cause &= timer_softc->config->irq_timer_wd_clr; |
| 417 | write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); |
| 418 | |
| 419 | val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); |
| 420 | val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); |
| 421 | write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); |
| 422 | |
| 423 | val = read_cpu_misc(RSTOUTn_MASK_ARMV7); |
| 424 | val &= ~RSTOUTn_MASK_WD; |
| 425 | write_cpu_misc(RSTOUTn_MASK_ARMV7, val); |
| 426 | |
| 427 | val = mv_get_timer_control(); |
| 428 | val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; |
| 429 | mv_set_timer_control(val); |
| 430 | } |
| 431 | |
| 432 | static void |
| 433 | mv_watchdog_disable_armv5(void) |
nothing calls this directly
no test coverage detected